1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to a method for fabricating a layer with a substantially smooth surface.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In most cases, a material may include a plurality of peaks and valleys upon its surface, which are associated with the surface roughness of the material. Such peaks and valleys may be visible by the naked eye or through an optical microscope, an electron microscope, or an atomic force microscope (AFM). In either embodiment, the surface roughness of a material may be characterized by the vertical distances between the bases of valleys and crests of their adjacent peaks. Since the dimensions of peaks and valleys may differ across a surface, calculating a statistical mean of a plurality of surface roughness measurements may yield a roughness that is more representative of the entire surface. For example, in some embodiments, an average of a plurality of surface roughness measurements may be calculated to produce a statistical mean of a material. In other embodiments, a root mean square of a plurality of surface roughness measurements may be calculated to produce a statistical mean of the material. In general, xe2x80x9croot mean squarexe2x80x9d may be referred to as a measure of the magnitude of a set of numbers or measurements.
In some cases, the surface roughness of one or more layers within a semiconductor topography may affect the operation of a device formed from such a topography. For example, in cases including magnetic random access memory (MRAM) devices, layers with relatively rough surfaces may undesirably cause a junction within a device to breakdown at a relatively low voltage. In particular, relatively rough surfaces of layers within MRAM devices including magnetic tunneling junctions (MTJ) may cause a breakdown of the junction at a low voltage. In some cases, breakdown at a relatively low voltage may cause the device to frequently malfunction, thereby decreasing the reliability and/or yield of the device. In addition or alternatively, the threshold voltage by which the device is activated may be lower and thus, the junction breakdown may inhibit the entire operation of the device in some cases. In general, the breakdown of a MTJ may be attributed to an uneven tunneling layer within the junction. Since tunneling layers within MTJs are typically very thin (e.g., approximately 15 angstroms or less), the unevenness of such a layer may be caused by relatively rough surfaces of underlying layers. Consequently, it may be beneficial to deposit a layer with substantially smooth surfaces under such a tunneling layer.
Conventional deposition processes, however, have limited capability to produce layers with substantially smooth surfaces. In particular, deposition techniques used in the semiconductor fabrication industry typically produce layers with relatively rough topographies. For example, conventional deposition techniques may yield a root mean square surface roughness that is greater than approximately 100 angstroms and in some cases, greater than approximately several thousand angstroms. xe2x80x9cRoot mean squarexe2x80x9d may refer to a result of a statistical calculation correlating a plurality of measurements as described above. Moreover, the accumulation of layers with such surface roughnesses may cause an upper layer to have an even greater surface roughness than may be produced by a particular deposition technique.
Therefore, it would be desirable to develop a method for fabricating semiconductor layers with substantially smooth surfaces. In particular, it may be advantageous to develop an MRAM device, which includes substantially smooth layers underlying a tunneling layer. Consequently, a method for reducing the likelihood of junction breakdown within a MRAM device may be developed.
The problems outlined above may be in large part addressed by a method for reducing the surface roughness of a metal layer. In particular, a method is provided for reducing the mean surface roughness of a metal layer. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. For example, a metal structure with a mean surface roughness less than approximately 10 angstroms may be obtained.
In yet other embodiments, the method may include depositing a fill layer upon a metal layer and subsequently polishing the fill layer. In some cases, polishing the fill layer may form a surface which includes portions of the metal layer and portions of the fill layer residing above the metal layer. In this manner, a semiconductor layer may be formed with fill material arranged around and within a plurality of peaks and valleys associated with the surface roughness of the metal layer. In such an embodiment, an upper surface of the fill layer may be substantially level with at least one of the peaks. In other cases, polishing the fill layer may include forming a surface in which the fill layer is arranged above an upper boundary of the metal layer-fill layer interface. In such an embodiment, the thickness of the fill layer arranged above the upper boundary may be less than the thickness of the interface.
As stated above, some embodiments of the method described herein may include polishing a metal layer arranged across approximately an entirety of a semiconductor topography to a level substantially above any layers arranged directly beneath the metal layer. In particular, the method may include depositing a metal layer upon a semiconductor topography, polishing the metal layer, and terminating the polishing process at a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material arranged laterally adjacent to the metal layer during the polishing process.
In either embodiment, the polishing process may include removing an upper portion of the metal layer such that no underlying layer is exposed. In some cases, polishing the metal layer may include removing between approximately 100 angstroms and approximately several thousand angstroms of the metal layer. In other embodiments, polishing the metal layer may include removing less than approximately 100 angstroms. In addition, in some cases the method may include patterning the metal layer. For example, in some embodiments, the method may include patterning the metal layer prior to the polishing process. In other embodiments, the method may include patterning the metal layer subsequent to the polishing process. In such an embodiment, the method may further include depositing a layer upon the polished metal layer prior to the patterning process. In general, the metal layer may include any metallic material, such as, but not limited to, aluminum, copper, tantalum, tungsten, titanium, or a metal alloy thereof. In addition or alternatively, the metal layer may include a metal nitride material, such as, but not limited to, titanium nitride or tungsten nitride.
In some embodiments, the method may include measuring a mean surface roughness of the metal layer subsequent to polishing the metal layer. In particular, measuring the mean surface roughness may include calculating an average surface roughness, a root mean square surface roughness, or any other statistical mean surface roughness of the metal layer. In some cases, the method may further include re-polishing the metal layer when the measured mean surface roughness is above a predetermined value. In this manner, a lower mean surface roughness may be obtained. In either case, polishing the metal layer may include reducing the mean surface roughness of the metal layer. For example, in some embodiments, polishing the metal layer may include reducing the mean surface roughness of the metal layer by a factor of at least approximately ten. More particularly, polishing the metal layer may include reducing the mean surface roughness of the metal layer by a factor between approximately ten and one hundred. In yet other embodiments, polishing the metal layer may include reducing the mean surface roughness of the metal layer by a factor of approximately fifty. In either embodiment, reducing the mean surface roughness may include reducing an average surface roughness, a root mean square surface roughness, or any other statistical mean surface roughness of the metal layer.
Consequently, polishing the metal layer may include producing a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer. For example, in some embodiments, polishing the metal layer may include producing a mean surface roughness of less than approximately 80 angstroms. In other embodiments, polishing the metal layer may include producing a mean surface roughness of less than approximately 10 angstroms. In yet other embodiments, polishing the metal layer may include producing a mean surface roughness between approximately 2 angstroms and approximately 3 angstroms.
Accordingly, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. For example, a semiconductor topography with a metal layer having a mean surface roughness of less than approximately 80 angstroms may be obtained. In some embodiments, the metal layer may include a mean surface roughness of less than approximately 10 angstroms. More specifically, in some embodiments the metal layer may include a mean surface roughness between approximately 2 angstroms and approximately 3 angstroms. In some embodiments, the metal layer may be arranged within a magnetic random access memory (MRAM) device. In such an embodiment, the metal layer may include a digit line of the MRAM device. Alternatively, the metal layer may include a layer within a magnetic tunneling junction of the MRAM device. In yet another embodiment, the metal layer may be arranged within a semiconductor topography that does not include a MRAM device.
In another embodiment of the semiconductor topography described herein, a layer within a semiconductor topography may include a metal surface having a plurality of peaks and valleys associated with the roughness of the metal surface and a fill material arranged within the valleys. In some cases, the fill material may be arranged upon the metal surface such that an upper surface of the fill material is substantially level with at least one of the peaks. In some embodiments, the fill material may include a dielectric; while in other embodiments, the fill material may include a conductive material. As in the embodiments described above, the metal surface may include any metallic material, such as, but not limited to, aluminum, copper, tantalum, tungsten, titanium, or a metal alloy thereof. In addition or alternatively, the metal surface may include a metal nitride, such as, but not limited to, titanium nitride or tungsten nitride. In this manner, the semiconductor layer may include one or more other metal surfaces adapted for electrical connection with a conductive layer. For example, in some cases, the one or more other metal surfaces may include the lowermost surface of the semiconductor structure and/or one or more sidewalls of the semiconductor structure. In addition, the metal surface may be arranged within a MRAM device. In such an embodiment, the metal surface may include a digit line of the MAM device. In yet other embodiments, the metal surface may include a layer within a magnetic tunneling junction of the MRAM device. Alternatively, the metal layer may be arranged within a semiconductor topography that does not include a MRAM device.
A method for processing a semiconductor topography with such a fill material may include, for example, depositing a fill layer upon a metal layer of the semiconductor topography and polishing the fill layer to form a surface. In some cases, the surface may include portions of the metal layer and portions of the fill layer residing above the metal layer. In such an embodiment, polishing may include removing less than approximately 100 angstroms of the metal layer. In other embodiments, the surface may include the fill layer arranged above an upper boundary of the metal layer-fill layer interface. In general, the interface may include laterally adjacent portions of a metal layer and a fill layer. The upper boundary of such an interface may be denoted by the upper most portion of the metal layer and laterally adjacent portions of the fill layer, while the lower boundary of the interface may be denoted by the lower most portion of the fill layer and laterally adjacent portions of the metal layer. In such an embodiment, in some cases the thickness of the fill layer arranged above the upper boundary may be less than the thickness of the interface. For example, in some embodiments the thickness of the interface may be at least approximately 70 angstroms and the thickness of the fill layer above the interface may be less than approximately 40 angstroms. However, larger or smaller thicknesses of the interface and fill layer above the interface may be appropriate depending on the design specifications of the device.
In either case, polishing the fill layer may include producing a mean surface roughness that is at least approximately 10 times less than a mean surface roughness of the metal layer prior to depositing the fill layer. In this manner, depositing and polishing the fill layer may include producing a mean surface roughness of less than approximately 10 angstroms, for example. In yet other embodiments, the method may include producing a mean surface roughness of less than approximately 4 angstroms, or more specifically between approximately 2 angstroms and approximately 4 angstroms. In some embodiments, the method may include measuring a mean surface roughness of the surface subsequent to polishing. In particular, measuring the mean surface roughness may include calculating an average surface roughness, a root mean square surface roughness, or any other statistical mean surface roughness of the metal layer. In cases when the measured mean surface roughness is above a predetermined value, the method may include re-polishing the surface. In this manner, a lower mean surface roughness may be obtained. In addition or alternatively, the method may include patterning the metal layer. In some cases, the patterning process may be conducted prior to polishing the fill layer. In other cases, the patterning process may be conducted subsequent to polishing the fill layer.
There may be several advantages for reducing the mean surface roughness of a metal layer as described herein. For example, metal layers with substantially smooth surfaces may allow a junction within a MRAM device formed therefrom to breakdown at a higher voltage than in an embodiment in which the junction is formed from layers with relatively rough surfaces. In particular, a MRAM device with substantially smooth layers below a tunneling layer of a magnetic tunneling junction (MTJ) may allow a substantially even and smooth tunneling layer to be formed, thereby preventing the junction from breakdown at a lower voltage. Consequently, the process window at which a MRAM device may be operated may be made larger by the inclusion of substantially smooth surfaces. As a result, the device may be operated at a lower current and consume less power. In addition or alternatively, the reliability and endurance of a device may be increased by the inclusion of smooth surfaces within the device. Furthermore, producing a substantially smooth metal layer may aid in producing substantially smooth layers above the metal layer, since the overlying layers will not conform to a relatively rough surface. Moreover, in the embodiment in which a fill layer is used to fill the valleys of the metal layer associated with the surface roughness of the metal layer, the method may reduce or eliminate the removal of the metal layer. In such an embodiment, the metal layer may be deposited within the design specifications of the device.